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MAC7200 Datasheet(PDF) 340 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 340 Page - Freescale Semiconductor, Inc |
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340 / 976 page ![]() Memory Map/Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 262 Freescale Semiconductor Register address: MCM Base + 0x0038 (PPMR1H) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R CD63 CD62 CD61 CD60 CD59 CD58 CD57 CD56 CD55 CD54 CD53 CD52 CD51 CD50 CD49 CD48 W Reset 000000000000000 0 15 14 13 12 11 10 9876543210 R CD47 CD46 CD45 CD44 CD43 CD42 CD41 CD40 CD39 CD38 CD37 CD36 CD35 CD34 CD33 CD32 W Reset 000000000000000 0 Figure 13-21. Peripheral Power Management Register 1 High (PPMR1H) Register address: MCM Base + 0x003c (PPMR1L) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 000000000000000 0 W Reset 000000000000000 0 15 14 13 12 11 10 9876543210 R 00000000000000 CDG 0 W Reset 000000000000000 0 Figure 13-22. Peripheral Power Management Register 1 Low (PPMR1L) Table 13-19. Peripheral Power Management (PPMR1H, PPMR1L) Field Description Field Description 63–32 CD[63:32] Clock Disable, Module Slot n. 0 The clock for this IPS module is enabled. 1 The clock for this IPS module is disabled. 31–2 Reserved, should be cleared. 1 CDG 0 The clock for the global IPS space is enabled. 1 The clock for the global IPS space is disabled. 0 Reserved, should be cleared.S |
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