MAC7200 datasheet(343/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

265

13.2.2.15.2

ECC Status Register (ESR)

The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC

events have been detected. The ESR signals the last, properly-enabled memory event to be detected. The

generation of the MCM ECC interrupt request is defined by the boolean equation:

MCM_ECC_IRQ

ECR[ER1BR] &

ESR[R1BC]// ram,

1-bit correction

ECR[EF1BR] &

ESR[F1BC]// flash, 1-bit correction

ECR[ERNCR] &

ESR[RNCE]// ram,

noncorrectable error

ECR[EFNCR] &

ESR[FNCE]// flash, noncorrectable error

where the combination of a properly-enabled category in the ECR and the detection of the corresponding

condition in the ESR produces the interrupt request.

The MCM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the

association between the ESR and the corresponding address and attribute registers, which are loaded on

each occurrence of an properly-enabled ECC event. If there is a pending ECC interrupt and another

properly-enabled ECC event occurs, the MCM hardware automatically handles the ESR reporting,

clearing the previous data and loading the new state and thus guaranteeing that only a single flag is

asserted.

To maintain the coherent software view of the reported event, the following sequence in the MCM error

interrupt service routine is suggested:

1. Read the ESR and save it.

2. Read and save all the address and attribute reporting registers.

3. Re-read the ESR and verify the current contents matches the original contents. If the two values

are different, go back to step 1 and repeat.

4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.

See Figure 13-24 and Table 13-21 for the ECC Status Register definition.

In the event that multiple status flags are signaled simultaneously, MCM records the event with the R1BC

as highest priority, then F1BC, then RNCE, and finally FNCE.

765

43210

R1BC

F1BC

RNCE

FNCE

Reset

00000000

Figure 13-24. ECC Status (ESR) Register

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