MAC7200 datasheet(347/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

269

The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are

{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.

13.2.2.15.4

Flash ECC Address Register (FEAR)

The FEAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the flash

memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the

address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and

FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored. See

Figure 13-26 and Table 13-23 for the Flash ECC Address Register definition.

Reserved, should be cleared.

6–0

ERRBIT[6:0]

Error Bit Position. The vector defines the bit position which is complemented to create the data inversion

on the write operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd

parity bit of the ECC code are inverted.

The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits

can be generated by setting this field to a value greater than the RAM width. For example, consider a

32-bit RAM implementation.

The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the actual

SRAM (32b data + 7b for ECC) = 39 bits. The following association between the ERRBIT field and the

corrupted memory bit is defined:

if ERRBIT = 0, then RAM[0] of the odd bank is inverted

if ERRBIT = 1, then RAM[1] of the odd bank is inverted

...

if ERRBIT = 31, then RAM[31] of the odd bank is inverted

if ERRBIT = 64,then ECC Parity[0] of the odd bank is inverted

if ERRBIT = 65,then ECC Parity[1] of the odd bank is inverted

...

if ERRBIT = 70,then ECC Parity[6] of the odd bank is inverted

For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.

Table 13-22. EEGR Field Descriptions (Continued)

Field

Description

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