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MAC7200 Datasheet(PDF) 350 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 350 Page - Freescale Semiconductor, Inc

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Memory Map/Register Definition
MAC7200 Microcontroller Family Reference Manual, Rev. 2
272
Freescale Semiconductor
13.2.2.15.7
Flash ECC Data Register (FEDR)
The FEDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR,
FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be
asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-29 and Table 13-26 for the Flash ECC Data Register definition.
13.2.2.15.8
RAM ECC Address Register (REAR)
The REAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the
RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-31 and Table 13-27 for the RAM ECC Address Register definition.
Figure 13-29. Flash ECC Data (FEDR) Register
Register address: MCM Base +0x5c
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
FEDR[31:16]
W
Reset
————————————————
15
14
13
12
11
10
9876543210
R
FEDR[15:0]
W
Reset
————————————————
Figure 13-30. Platform Flash ECC Data (PFEDR) Register
Table 13-26. FEDR Field Descriptions
Field
Description
31–0
FEDR
Flash ECC Data Register. This 64-bit register contains the data associated with the faulting access of the
last, properly-enabled flash ECC event. The register contains the data value taken directly from the data
bus.



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