MAC7200 datasheet(353/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

275

the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,

RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status

This register can only be read from the IPS programming model; any attempted write is ignored. See

Figure 13-33 and Table 13-30 for the RAM ECC Master Number Register definition.

13.2.2.15.11 RAM ECC Attributes Register (REAT)

The REAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled

ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event

in the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,

RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status

This register can only be read from the IPS programming model; any attempted write is ignored. See

Figure 13-34 and Table 13-31 for the RAM ECC Attributes Register definition.

765

43210

0000

REMR[3:0]

Reset

0000

————

Figure 13-33. RAM ECC Master Number (REMR) Register

Table 13-30. REMR Field Descriptions

Field

Description

7–4

Reserved, should be cleared.

3–0

REMR[3:0]

RAMECC Master Number Register. This 4-bit register contains the AXBS bus master number of the

faulting access of the last, properly-enabled RAM ECC event.

765

43210

Write

Size[2:0]

Protection[3:0]

Reset

————————

Figure 13-34. RAM ECC Attributes (REAT) Register

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