MAC7200 datasheet(356/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

278

Freescale Semiconductor

13.2.2.16.2

Core Fault Location/Interrupt Enable Register (CFLOC1)

The CFLOC1 is an 8-bit register with multiple functions for SPP implementations. For SPP_Ref_CFx

designs, this register contains a 1-bit enable to generate an error interrupt on the detection of a faulted

processor AHB system bus cycle. See Table 13-37 and Table 13-34 for the Core Fault Location Register

definition.

CFADR[31:16]

Reset

————————————————

9876543210

CFADR[15:0]

Reset

————————————————

Figure 13-36. Core Fault Address (CFADR) Register

Table 13-33. CFADR Field Descriptions

Field

Description

31–0

CFADR[31:0]

Core Fault Address Register. This 32-bit register contains the faulting address of the last core data access

terminated with an error response.

765

43210

0000000

ECFEI

Reset

—

0000000

Figure 13-37. Core Fault Location 1 (CFLOC1) Register

Table 13-34. Core Fault Location 1 (CFLOC1) Field Descriptions

Field

Description

7–1

Reserved, should be cleared.

ECFEI

Enable Core Fault Error Interrupt.

0 Do not generate an error interrupt on a faulted processor system bus cycle.

1 Generate an error interrupt on a faulted processor system bus cycle.

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