MAC7200 datasheet(355/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

277

13.2.2.16 Core Data Fault Recovery Registers

To aid in recovery from certain types of data access errors, the MCM module optionally supports a number

of registers which capture access address, attribute and data information on bus cycles terminated with an

error response. These registers can then be read during the resulting exception service routine and the

appropriate recovery performed.

The details on the core fault recovery registers are provided in the subsequent sections. It is important to

note these registers are used to capture fault recovery information only on data access faults, i.e., no

information is captured on instruction fetch faults. If the design does not include the fault recovery

registers, these addresses are reserved locations within the MCM’s programming model.

13.2.2.16.1

Core Fault Address Register (CFADR)

The CFADR is a 32-bit register for capturing the address of the last core data access which was terminated

with an error response. This register can only be read from the IPS programming model; any attempted

write is ignored. See Figure 13-36 and Table 13-33 for the Core Fault Address Register definition.

REDR[31:16]

Reset

————————————————

9876543210

RREDR[15:0]

Reset

————————————————

Figure 13-35. RAM ECC Data (REDR) Register

Table 13-32. REDR Field Descriptions

Field

Description

31–0

REDR[31:0]

RAM ECC Data Register. This 32-bit register contains the data associated with the faulting access of the

last, properly-enabled RAM ECC event. The register contains the data value taken directly from the data

bus.

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