MAC7200 datasheet(351/976 Pages) FREESCALE

351 / 976 page

Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

273

13.2.2.15.9

RAM ECC Syndrome Register (RESR)

The RESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC event in

the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM

causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,

REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register

to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored. See

Figure 13-32 and Table 13-28 for the RAM ECC Syndrome Register definition.

REAR[31:16]

Reset

————————————————

9876543210

RREAR[15:0]

Reset

————————————————

Figure 13-31. RAM ECC Address (REAR) Register

Table 13-27. REAR Field Descriptions

Field

Description

31–0

REAR[31:0]

RAM ECC Address Register. This 32-bit register contains the faulting access address of the last,

properly-enabled RAM ECC event.

765

43210

RRESR[7:0]

Reset

————————

Figure 13-32. RAM ECC Syndrome (RESR) Register

MAC7200 Datasheet(PDF) 351 Page - Freescale Semiconductor, Inc