MAC7200 datasheet(348/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

270

Freescale Semiconductor

13.2.2.15.5

Flash ECC Master Number Register (FEMR)

The FEMR is a 4-bit register for capturing the AXBS bus master number of the last, properly-enabled ECC

event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in

the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,

FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register

to be asserted.

This register can only be read from the IPS programming model; any attempted write is ignored. See

Figure 13-27 and Table 13-24 for the Flash ECC Master Number Register definition.

FEAR[31:16]

Reset

————————————————

9876543210

FEAR[15:0]

Reset

————————————————

Figure 13-26. Flash ECC Address (FEAR) Register

Table 13-23. FEAR Field Descriptions

Field

Description

31–0

FEAR[31:0]

Flash ECC Address Register. This 32-bit register contains the faulting access address of the last,

properly-enabled flash ECC event.

765

43210

0000

FEMR[3:0]

Reset

0000

————

Figure 13-27. Flash ECC Master Number (FEMR) Register

Table 13-24. PFEMR Field Descriptions

Field

Description

7–4

Reserved, should be cleared.

3–0

FEMR[3:0]

Flash ECC Master Number Register. This 4-bit register contains the AXBS bus master number of the

faulting access of the last, properly-enabled flash ECC event.

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