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MAC7200 Datasheet(PDF) 359 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 359 Page - Freescale Semiconductor, Inc |
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359 / 976 page ![]() MCM as Implemented on MAC7200 MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 281 13.3 MCM as Implemented on MAC7200 13.3.1 MCM Introduction The Miscellaneous Control Module implements a number of system level features, including the following: • Program-visible information on the device configuration and revision. • Software watchdog timer (SWT) with programmable system reset or interrupt response which runs on a separate, asynchronous clock. The SWT also supports a windowed time period, requiring the writing of the watchdog key within a specified time window. The source for the SWT clock is controlled by the Clock and Reset Generator. • Wakeup control for entering and exiting sleep modes, including an enable and an interrupt priority mask. • Access address information for faulted memory accesses. When a bus abort occurs in the system, the exact cause of the abort can be determined by reading the Core Data Fault Recovery Registers in the MCM. • Address map for the crossbar switch (AXBS), which is used to steer access to the Crossbar slave ports in order to provide remapping operations. Following Reset, the contents of the AAMR register are determined by the mode entered as a result of the default slave mapping, but may be configured by the application code in order to remap the Flash, External bus and RAM between AXBS Slave Port 0 and Port 1. Please refer to Chapter 9, “Device Memory Map” for further details. Register address: MCM Base + 0x7c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R CFDTR[31:16] W Reset ———————————————— 15 14 13 12 11 10 9876543210 R CFDTR[15:0] W Reset ———————————————— Figure 13-40. Core Fault Data (CFDTR) Register Table 13-37. CFDTR Field Descriptions Field Description 31–0 CFDTR[31:0] Core Fault Data Register. This 32-bit register contains the data associated with the faulting access of the last AMBA-AHB write access. The register contains the data value taken directly from the device write data bus. |
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