MAC7200 datasheet(363/976 Pages) FREESCALE

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MCM as Implemented on MAC7200

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

285

If any part of a read or write falls within an aborted region, the entire transfer is aborted. For example, a

32-bit read or write to address $0074 would be aborted.

In addition, the following transfers will be aborted:

•

Byte write to 16-bit reg (swtcr, eegr)

•

Byte or word write to 32-bit reg (paamr, ppmr*)

Supervisor Access: Unused

13.3.5

MCM Differences from MAC71xx

•

Obsoleted use of the MRSR register

•

Added ECC related registers and reporting

— General ECC: Added ECR, ESR, EEGR registers

— Flash ECC: Added FEAR, FEMR, FEAT, FEDRH, FEDRL registers

— SRAM ECC: Added REAR, REDRH, REDRL registers

$0016-$0017

$0018-$001a

$001b

$001c-$001e

$001f-$0027

$0028-$002a

$002b

$002c-$0042

$0043

$0044-$0046

$0047

$0048-$0049

$004a-$004b

$004c-$004f

$0050-$0053

$0044-$0046

$0047

$0054-$0055

$0056-$0063

$0064

$0065-$0073

$0074-$0075

$0076-$0077

$0078-$007b

$007c-$007f

$0080-$3fff

Table 13-41. MCM Bus Aborts (Continued)

Abort

Allowed

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