MAC7200 datasheet(362/976 Pages) FREESCALE

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MCM as Implemented on MAC7200

MAC7200 Microcontroller Family Reference Manual, Rev. 2

284

Freescale Semiconductor

13.3.2.7

AXBS Address Map Register (AAMR)

This 32-bit register controls the address mapping for each of the 8 possible AXBS slaves. Please refer to

Section 9.16.4, “Programming the AAMR register in the MCM” for more details on the AAMR

functionality.

13.3.2.8

Misc. User-Defined Control Register (MUDCR)

The MUDCR register will be used on the MAC72xx as the Write Access Control (WACC) register for the

main Flash array. Please refer to Section 18.7.4.2, “Flash MCM Registers” for more information on the

WACC register.

13.3.2.9

ECC

Both the on-chip RAM and Flash memories include ECC with 2-bit detection/1-bit correction. The MCM

ECC registers include a variety of features to utilize the ECC, including full reporting features. Because

the ARM7 core supports Pre-fetch (Instruction) and Data aborts, all code for servicing both of these

exceptions should make use of the ECC reporting registers in the MCM.

13.3.2.10 Fault Registers

The MCM provides several registers that can be used by the Pre-fetch Abort and Data Abort exception

handlers to determine the exact location and type of an illegal instruction or data fetch. Please refer to

Section 7.2.4, “Prefetch (Instruction) Abort” for a list of bus abort sources.

13.3.2.11 Non-Maskable Interrupt (NMI)

Please refer to Section 7.3.4, “Non-Maskable Interrupt (NMI)” for details on the Non-Maskable Interrupt.

The MCM allows enabling/disabling of the NMI feature, as well as polarity configuration and NMI status

information.

13.3.3

MCM External Pins

There are no MCM signals that drive or are driven from MCU pins.

13.3.4

MCM Bus Aborts

The MCM module supports Peripheral Bus bus aborts, and enforces the following memory map:

Table 13-41. MCM Bus Aborts

Abort

Allowed

$0000-$000b

$000c-$000e

$000f

$0010-$0012

$0013

$0014-$0015

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