MAC7200 datasheet(365/976 Pages) FREESCALE

365 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

287

Chapter 14

SPP Interrupt Controller Module for ARM (SPP_INTC_ARM)

14.1

Introduction

14.1.1

Overview

The ARM_INTC is a highly-programmable interrupt controller, collecting both on-platform and

off-platform interrupt requests, mapping the requests into 16 priority levels, and then signalling the ARM

processor when a properly enabled non-masked request is active. In response to the service routine’s

memory mapped interrupt acknowledge read cycle, the controller returns a unique vector for each interrupt

request and automatically manages masking of lower level requests. As any interrupt source can be

assigned to any of the sixteen priority levels, and the interrupt controller enables the definition of which

priority levels are assigned to Fast or Normal interrupts, each interrupt source can be selected to generate

either a Fast or Normal interrupt to the core by its assigned level.

Normal or Fast interrupts can enable the cores bus master priority to be elevated on the crossbar switch to

assist with accelerating the handling of interrupts of the specified type.

The MAC7200 family of devices implement one interrupt controller which supports 64 interrupt requests.

The interrupt controller is accessed via the peripheral bus for both configuration and for fetching the

interrupt vector.

Consult Section 14.7, “The Interrupt Controller Module (INTC)” for information about the vector

interrupt controller implemented in the core Platform and Chapter 7, “Exceptions” for a list of the possible

interrupt sources in the system.

14.2

INTC Features

•

64 vectored interrupt sources.

•

Interrupt sources available from internal peripherals, eDMA controller, software watchdog timer

and external sources.

•

Supports 16 interrupt levels (0-15) with 64 priorities per level (1-64), to allow maximum flexibility

in configuring the system. Every interrupt source can be programmed to any interrupt level.

Priorities within a level are hard-coded in the MCU.

•

Multiple level interrupt nesting.

•

Hardware support for first nesting level.

•

Normal and Fast interrupts supported with software programmability of sources for both Fast and

Normal Interrupts

•

Memory Map: 32-bit peripheral with 256 bytes, byte addressable

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