MAC7200 datasheet(369/976 Pages) FREESCALE

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The Interrupt Controller Module (INTC)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

291

Figure 14-1. INTC Block Diagram

14.7.1

Review of ARM Interrupt Architecture

Before continuing with the specifics of the platform interrupt controller, a brief review of the interrupt

architecture of the ARM core family is appropriate.

ARM cores support two direct interrupt request signals: a FIQ (fast interrupt request) and an IRQ (normal

interrupt request). These two inputs are prioritized by the hardware with the FIQ being higher priority than

the IRQ. Like most processor cores, interrupts are sampled once per instruction. If the FIQ input signal is

asserted and enabled in the processor’s status register (CPSR), then the core suspends normal execution

and initiates processing of a fast interrupt exception.

During exception processing, the contents of two key registers are copied into “shadow” or banked

registers. Specifically, the current program counter (R15) is copied into the banked copy of the R14 link

INTC

IPS

Bus

ips_wdata

intfrc

imr

ipr

ips_addr

decode

ipi_int[63:0]

lp_int_mask[*]

icr0...3

icr60...63

Vector

Gen

_wakeup _active_* ints to core

ips_rdata

mux

Prioritization &

Level Masking

Level

Conversion

clmask

slmask

iack

IPS Bus

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