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MAC7200 Datasheet(PDF) 372 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 372 Page - Freescale Semiconductor, Inc |
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372 / 976 page  Memory Map/Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 294 Freescale Semiconductor The platform’s IPS memory map reserves a contiguous 64 KByte space for the interrupt controller(s). Figure 14-5 shows the 256-byte memory map for a single interrupt controller. For designs with multiple controllers, see Figure 14-6. 14.8.1 Register Descriptions 14.8.1.1 IPR[63:0] - Interrupt Pending Register (IPRH, IPRL) The IPRH and IPRL registers are each 32 bits in size, and provide a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. The state of 0x006c Interrupt Control Register 44 (ICR44) Interrupt Control Register 45 (ICR45) Interrupt Control Register 46 (ICR46) Interrupt Control Register 47 (ICR47) 0x0070 Interrupt Control Register 48 (ICR48) Interrupt Control Register 49 (ICR49) Interrupt Control Register 50 (ICR50) Interrupt Control Register 51 (ICR51) 0x0074 Interrupt Control Register 52 (ICR52) Interrupt Control Register 53 (ICR53) Interrupt Control Register 54 (ICR54) Interrupt Control Register 55 (ICR55) 0x0078 Interrupt Control Register 56 (ICR56) Interrupt Control Register 57 (ICR57) Interrupt Control Register 58 (ICR58) Interrupt Control Register 59 (ICR59) 0x007c Interrupt Control Register 60 (ICR60) Interrupt Control Register 61 (ICR61) Interrupt Control Register 62 (ICR62) Interrupt Control Register 63 (ICR63) 0x0080-0x00dc Reserved 0x00e0 Reserved 0x00e4 Reserved 0x00e8 Reserved 0x00ec IRQ Acknowledge {IRQIACK) Reserved 0x00f0 FIQ Acknowledge (FIQIACK) Reserved 0x00f4 Reserved 0x00f8 Reserved 0x00fc Reserved Table 14-6. Multiple Interrupt Controller IPS Memory Map Configuration Offset for intc01 1. The offsets for intc1, intc2 and the IACK addresses are relative to the base of intc0. Offset for intc1 Offset for intc2 IACK Addresses 1 controller 0x0000 — — 0x00ec, 0x00f0 2 controllers 0x0000 +0x4000 — 0xc0ec, 0xc0f0 3 controllers 0x0000 +0x4000 +0x8000 0xc0ec, 0xc0f0 Table 14-5. INTC 32-bit Memory Map (Continued) |
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