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MAC7200 Datasheet(PDF) 375 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 375 Page - Freescale Semiconductor, Inc |
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375 / 976 page ![]() Memory Map/Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 297 14.8.1.3 INTFRC[63:0] - Force Interrupt Register (INTFRCH, INTFRCL) The INTFRCH and INTFRCL registers are each 32 bits in size, and provide a mechanism to allow software generation of interrupts for each possible source for functional or debug purposes. The system design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRC register. In some cases, the handling of an interrupt request may cause critical processing by the service routine along with the scheduling (using the INTFRC register) of a lower-priority interrupt request to be processed at a later Register address: INTC_Offset + 0x08 (IMRH), + 0x0c (IMRL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W RESET: 1111111111111111 15 14 13 12 11 10 9876543210 R W RESET: 1111111111111111 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W RESET: 1111111111111111 15 14 13 12 11 10 9876543210 R W RESET: 1111111111111111 = Unimplemented or Reserved Figure 14-3. Interrupt Mask (IMRH, IMRL) Registers Table 14-8. Interrupt Mask (IMRH, IMRL) Field Descriptions Name Description IMRn, n = 0,... 63 Interrupt Mask Register n 0 The interrupt request n is enabled. 1 The interrupt request n is disabled, i.e., masked. |
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