MAC7200 datasheet(378/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

300

Freescale Semiconductor

14.8.1.5

Set Interrupt Mask (SIMR) Register

The SIMR register provides a simple memory-mapped mechanism to set a given bit in the IMR{H,L}

registers to disable (“mask”) a given interrupt request. The data value on a register write causes the

corresponding bit in the IMR{H,L} register to be set. A data value greater than 63 provides a global set

function, forcing the entire contents of IMR{H,L} to be asserted, masking all interrupts. Reads of this

This register is provided so interrupt service routines can easily mask the given interrupt request without

the need to perform a read-modify-write sequence on the IMR{H,L}.

See Figure 14-6 and Figure 14-11 for the SIMR definition.

EMASK

Enable Hardware Level Masking

If set, the INTC automatically loads the level of an interrupt request into the CLMASK (current level mask)

when an acknowledge is performed. At the exact same cycle, the value of the current interrupt level mask is

saved in the SLMASK (saved level mask) register.

This feature can be used to support software-managed nested interrupts. The value of SLMASK register

should be read from the INTC and saved in the interrupt stack frame in memory, and restored near the service

routine’s exit.

If cleared, the INTC does not perform any automatic masking of interrupt levels.

4–0

FIQDEF

FIQ Interrupt Level Definition

This 5-bit field defines the mapping of the 16 interrupt levels into the FIQ output signal. The field is defined as:

0x00 = Levels 0 - 15 are mapped as FIQs

0x01 = Levels 1 - 15 are mapped as FIQs

0x02 = Levels 2 - 15 are mapped as FIQs

0x03 = Levels 3 - 15 are mapped as FIQs

0x04 = Levels 4 - 15 are mapped as FIQs

0x05 = Levels 5 - 15 are mapped as FIQs

0x06 = Levels 6 - 15 are mapped as FIQs

0x07 = Levels 7 - 15 are mapped as FIQs

0x08 = Levels 8 - 15 are mapped as FIQs

0x09 = Levels 9 - 15 are mapped as FIQs

0x0a = Levels 10 - 15 are mapped as FIQs

0x0b = Levels 11 - 15 are mapped as FIQs

0x0c = Levels 12 - 15 are mapped as FIQs

0x0d = Levels 13 - 15 are mapped as FIQs

0x0e = Levels 14 - 15 are mapped as FIQs

0x0f = Level

is mapped as FIQ

0x1- = No levels are mapped as FIQs; all are IRQs

Table 14-10. Interrupt Configuration (ICONFIG) Field Descriptions

Name

Description

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