MAC7200 datasheet(377/976 Pages) FREESCALE

377 / 976 page

Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

299

14.8.1.4

Interrupt Configuration (ICONFIG) Register

The ICONFIG register defines the operating configuration for the INTC module. See Figure 14-5 and

Figure 14-10 for the ICONFIG definition.

76543210

FIQDEF[4:0]

RESET:

10100000

= Unimplemented or Reserved

Figure 14-5. Interrupt Configuration (ICONFIG) Register

Table 14-10. Interrupt Configuration (ICONFIG) Field Descriptions

Name

Description

EFIQPRI

Enable Core’s Priority Elevation on FIQ

If set, the assertion of an FIQ request to the core causes the processor’s bus master priority to be temporarily

elevated in the platform’s crossbar switch arbitration logic. The processor’s bus master arbitration priority

remains elevated until the FIQ request is negated. If round-robin arbitration is enabled, this bit has no effect.

If cleared, the assertion of an FIQ request does not affect the processor’s bus master priority.

EIRQPRI

Enable Core’s Priority Elevation on IRQ

If set, the assertion of an IRQ request to the core causes the processor’s bus master priority to be temporarily

elevated in the platform’s crossbar switch arbitration logic. The processor’s bus master arbitration priority

remains elevated until the IRQ request is negated. If round-robin arbitration is enabled, this bit has no effect.

If cleared, the assertion of an IRQ request does not affect the processor’s bus master priority.

MAC7200 Datasheet(PDF) 377 Page - Freescale Semiconductor, Inc