MAC7200 datasheet(382/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

304

Freescale Semiconductor

14.8.1.9

Interrupt Control Register n (ICRn), n = 0, 1, 2,..., 63

The ICRn registers contain the software-defined interrupt level for each interrupt request. Each ICRn

contains a 4-bit interrupt level [0-15]. These registers are cleared by reset and should be programmed with

the appropriate levels before interrupts are enabled.

When multiple interrupt requests are programmed to the same level number, they are processed in a

descending request number order. As an example, if requests 63, 62, 2, 1 are programmed to a common

level, request 63 is processed first, then request 62, then request 2 and finally request 1.

This definition allows software maximum flexibility in grouping interrupt request sources within any

given priority level.

See Figure 14-10 and Figure 14-15 for the ICRn definition.

14.8.1.10 IRQ Interrupt Acknowledge Register (IRQIACK)

The IRQIACK register is a read-only resource containing the vector number of the interrupt request

currently being processed. It is typically read early in an IRQ interrupt service routine. There is a fixed

association between the vector number returned in the IRQIACK register and the physical interrupt request

input signal, namely:

Table 14-14. Saved Level Mask (SLMASK) Field Descriptions

Name

Description

4–0

SLMASK

Saved Level Mask

This 5-bit field is treated as a signed integer within the range [-1, 0, 1,..., 15]. The value defines the saved level

mask. See the CLMASK field definition for more information on the specific values.

76543210

0000

Level[3:0]

RESET:

0000

= Unimplemented or Reserved

Figure 14-10. Interrupt Control Register n (ICRn)

Table 14-15. Interrupt Control Register n (ICRn) Field Descriptions

Name

Description

3–0

Level

Interrupt Request Level

This 4-bit field maps the given interrupt request to one of 16 levels, where 0x0 is the lowest priority level and 0xf

is the highest priority level.

If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgment of a level-n request forces the

controller to automatically mask all interrupt requests of level-n and lower.

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