MAC7200 datasheet(385/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

307

addresses and uses the interrupt vector number as an index into this table so that execution in the

appropriate service routine can begin as quickly as possible.

Refer to the INTC block diagram, Figure 14-1, for the subsequent discussion.

14.9.1.1

Interrupt Recognition

The interrupt controller continuously examines the request sources (the IPR register) and the interrupt

mask register (IMR) to determine if there are active requests. This is the recognition phase. The Interrupt

Force Register (INTFRC) also factors into the generation on an active request. An active request

(assuming the hardware masking is enabled) is defined by the following boolean equation:

active_request[n]

= (IPR[n]

& ~IMR[n]

INTFRC[n]) & (ICRn > CLMASK)

14.9.1.2

Interrupt Prioritization and Level Masking

As an active request is detected, it is first translated into the programmed interrupt level. Next, the

appropriate level masking is performed, if this feature is enabled. Recall the level of the active request must

be greater than the current mask level before it is signaled to the processor. The resulting 16-bit unmasked

decoded priority level (intc_active_level[15:0]) is then driven out of the interrupt controller. The decoded

priority levels from all the interrupt controllers are logically summed together and the highest priority

interrupt level is then encoded into the 2-bit FIQ/IRQ signals that are sent to the processor core during this

prioritization phase. The mapping of the interrupt levels into the 2-bit FIQ/IRQ signals (the level

conversion) is controlled by the ICONFIG[FIQDEF] field.

14.9.1.3

Vector Generation during IACK

Once the core has sampled for pending interrupts and completed interrupt exception processing, it begins

execution of the interrupt service routine (ISR) and typically generates a byte-sized operand read from the

controller known as an interrupt acknowledge cycle. The type of interrupt request being acknowledged

(FIQ or IRQ) determines the access address. The IACK transfer is a memory-mapped byte read via the

AIPS controller of the FIQIACK or IRQIACK register,which, in the case of multiple interrupt controller

instantiations, is routed into a separate interrupt arbiter module that determines the interrupt controller that

gets the IACK transfer based upon which controller has the appropriate level pending. Interrupt arbitration

priority is discussed in Section Figure 14.9.1.4. Next, the interrupt controller determines the highest

unmasked level for the type of interrupt being acknowledged, and generates an 8-bit interrupt vector for

that request to complete the cycle. The 8-bit interrupt vector is formed using the following algorithm:

For intc0,

vector_number =

64 + ipi_int[x]

For optional intc1,

vector_number = 128 + ipi_int[x]

For optional intc2,

vector_number = 192 + ipi_int[x]

where the bit position [x] within the ipi_int[63:0] source directly determines the vector number. Vector

numbers 0 - 63 are reserved for the processor and its internal exceptions. Thus, the following mapping of

bit positions to vector numbers applies for the mandatory intc0:

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