MAC7200 datasheet(387/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

309

interrupt controllers. The interrupt arbiter is completely combinatorial and does not need to be configured,

however the interrupt controller does have some requirements when more than one is present.

First, the Interrupt Configuration Register (ICONFIG) must be loaded with the exact same value in all

instantiations of the interrupt controller. This is accomplished by writing to the ICONFIG register of intc0.

This single write is then broadcast to all the controllers in the device via the interrupt arbiter.

Second, all reads and writes of the Current Level Mask (CLMASK) and Saved Level Mask (SLMASK)

these two control registers is maintained in intc0.

Third, the interrupt controllers have a fixed priority, where intc0 is the highest, and intc2 is the lowest. The

net effect is the combined interrupt levels across the multiple controllers are defined as (highest to lowest):

intc0:

level 15

intc1:

level 15

intc2:

level 15

intc0:

level 14

intc1:

level 14

intc2:

level 14

intc0:

level 0

intc1:

level 0

intc2:

level 0

The resulting logic to steer an IACK read in a three-controller configuration using the

intcx_active_level[15:0] output vector is defined in Figure 14-18:

14.9.2

Performance

There are two key performance parameters for the interrupt controller: latency from the assertion of an

interrupt request, and vector generation timing.

Table 14-18. Global IACK Steering Algorithm1 (3 Controllers)

1. “-” indicates a don’t care logic value.

intc0_active_level

[15:0]

intc1_active_level

[15:0]

intc2_active_level

[15:0]

Level

Acknowledged

IACK Steering

1---------------

----------------

Level 15

Route to intc0

0---------------

1---------------

----------------

Level 15

Route to intc1

0---------------

1---------------

Level 15

Route to intc2

01--------------

0---------------

Level 14

Route to intc0

00--------------

01--------------

0---------------

Level 14

Route to intc1

00--------------

01--------------

Level 14

Route to intc2

...

0000000000000001

00000000000000-

000000000000000-

Level 0

Route to intc0

0000000000000000

000000000000001

000000000000000-

Level 0

Route to intc1

0000000000000000

000000000000000

0000000000000001

Level 0

Route to intc2

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