MAC7200 datasheet(388/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

310

Freescale Semiconductor

As can be seen in the INTC block diagram (Figure 14-1), there are two levels of hardware registers

between the assertion of an interrupt request on the ipi_int[63:0] input and the posting of the FIQ/IRQ

request to the processor core. Thus, if an interrupt request is first asserted in cycle i, then the first assertion

of a properly-enabled request to the processor core occurs in cycle i+2. The processor’s sampling of the

interrupt request signals is then dependent on the instruction stream being executed. For more information

on the core behavior, see the appropriate ARM reference manual. As an example, see Section 2.9, page 69

of the ARM7TDMI Technical Reference Manual, Rev. 4.

As the IACK cycle is performed during the interrupt service routine, it appears as a normal IPS read cycle,

and requires three platform cycles in the AMBA-AHB data phase (2 wait-states).

14.10 Initialization/Application Information

14.10.1 Initialization

The interrupt controller’s reset state has all requests masked via the IMR. Before any interrupt requests are

enabled, the following steps must be taken:

1. The ICONFIG register needs to be set to the desired system configuration.

2. All the ICRn registers need to be programmed with the appropriate interrupt levels.

3. The reset value for the Level Mask registers (CLMASK and SLMASK) are set to -1, the value with

no levels masked. Typically, these registers do not need to be modified before interrupts are

enabled.

4. The appropriate interrupt vector tables and interrupt service routines must be loaded into memory.

Additionally, the memory address pointers for the FIQ and IRQ stacks loaded into the

R13_{fiq,irq} registers.

5. Enable the interrupt requests by clearing the appropriate bits in the IMR and the CPSR[F,I] .

14.10.2 Typical Applications

In many real-time system designs, a typical configuration for supporting priority-based preemptive task

scheduling requires only a single interrupt signal to the processor core. Stated differently, the two levels of

interrupt support provided by an ARM core (FIQ/IRQ) are not necessarily required, and a single level is

sufficient. For ARM cores with only a single interrupt level is implemented, the FIQ exception mode is

typically the one to be used since it provides significantly more hardware resources for the interrupt

processing than IRQ.

By setting ICONFIG[FIQDEF] = 0x00, all interrupt requests are mapped into the FIQ request signal, and

the IRQ core functionality is completely unused.

Another common configuration may chose to define certain “non-maskable” interrupt requests. Typically,

these requests are programmed as level 15, and would be logically connected to the FIQ core input. In this

configuration, priority levels 0-14 would then be available for use of normal (IRQ) requests.

For applications where the wakeup functionality is used, the interrupt controller includes logic that limits

the largest value of the interrupt mask level to “maximum – 1" so the controller can always generate an

sleep mode exit. Thus, if ipg_lp_int_mask is set to the maximum value, the interrupt controller converts

MAC7200 Datasheet(PDF) 388 Page - Freescale Semiconductor, Inc