MAC7200 datasheet(392/976 Pages) FREESCALE

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Introduction

MAC7200 Microcontroller Family Reference Manual, Rev. 2

314

Freescale Semiconductor

15.1.1

Overview

The crossbar switch bus connects the bus masters and bus slaves using a crossbar switch structure. This

structure allows bus masters to simultaneously access different bus slaves with no interference while

providing arbitration among the bus masters when they access the same slave. A variety of bus arbitrations

methods and attributes may be programmed on a bus slave by bus slave basis.

15.1.2

Features

The crossbar switch bus includes these distinctive features:

•

Symmetric crossbar bus switch implementation

— Allows concurrent accesses from different masters to different slaves

— Slave arbitration attributes configured on a slave by slave basis

•

The crossbar switch bus is 32 bits wide and supports byte, half-word (2byte), word (4byte), and

16byte burst transfers

•

32-bit address bus width, 32-bit data bus width

•

Crossbar switch bus operates at a 1-to-1 clock frequency with the bus masters

•

Support for AHB v2.0 AHB-Lite bus protocol

•

Up to 8x8 simultaneous Master => Slave connections

•

Each Slave Port is individually configurable via a Peripheral Bus interface

•

Memory Map: 32-bit peripheral with 256 bytes per slave port, word addressable only

•

Each slave port has a 3-bit base address, to select a 512Mb address space within the 4Gb

addressable space. All combinations of master/slave are valid. The crossbar switch can support

simultaneous master transactions, as long as the slave being accessed is different.

15.1.3

AXBS Integration

The AXBS is integrated with the following configuration:

•

Alternate Master Priority (AMPR) register is not enabled

Table 15-1. Crossbar Slave Port Addresses

Slave Port

Address Range

$0000_0000 - $1FFF_FFFF

$2000_0000 - $3FFF_FFFF

$4000_0000 - $5FFF_FFFF

$6000_0000 - $7FFF_FFFF

$8000_0000 - $9FFF_FFFF

$A000_0000 - $BFFF_FFFF

$C000_0000 - $DFFF_FFFF

$E000_0000 - $FFFF_FFFF

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