MAC7200 datasheet(394/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

316

Freescale Semiconductor

The registers are fully decoded and a bus error response is returned if an unimplemented location is

accessed within the crossbar switch bus.

The slave registers also feature a bit, which when written with a 1, will prevent the registers from being

written to again. The registers will still be readable, but future write attempts will have no effect on the

registers and will be terminated with an error response.

Table 15-3 is the memory map for the crossbar switch bus program-visible registers.

15.4

This section consists of register descriptions for the crossbar switch bus.

15.4.1

Priority Register

The Priority Register (PR) sets the priority of each master port on a per slave port basis and resides in each

slave port.

Table 15-3. Module Memory Map

Offset from

crossbar_base

Access

0x000

Priority Register for Flash Controller Slave port (PR_FC)

word (4byte)

0x010

Control Register for Flash Controller Slave port (CR_FC)

word (4byte)

0x100

Priority Register for FlexBus Slave port (PR_FB)

word (4byte)

0x110

Control Register for FlexBus Slave port (CR_FB)

word (4byte)

0x300

Priority Register for RAM Controller Slave port (PR_RC)

word (4byte)

0x310

Control Register for RAM Controller Slave port (CR_RC)

word (4byte)

0x500

Priority Register for external AHB Slave port (PR_AHB)

word (4byte)

0x510

Control Register for external AHB Slave port (CR_AHB)

word (4byte)

0x700

Priority Register for Peripheral Controller Slave port (PR_PC)

word (4byte)

0x710

Control Register for Peripheral Controller Slave port (CR_PC)

word (4byte)

Table 15-4. Priority Register Summary

PR_FC

PR_FB

PR_RC

PR_AHB

PR_PC

Priority Register for Slave Port to Flash Controller

Priority Register for Slave Port to FlexBus

Priority Register for Slave Port to RAM Conttroller

Priority Register for Slave Port to external AHB

Priority Register for Slave Port to Peripheral Controller

crossbar_base + 0x000

crossbar_base + 0x100

crossbar_base + 0x300

crossbar_base + 0x500

crossbar_base + 0x700

Bit

Name

Reserved

Type

rrr

Reset

000

Bit

987

432

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