MAC7200 datasheet(393/976 Pages) FREESCALE

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External Signal Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

315

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Alternate Slave General Purpose (ASGPR) register is not enabled

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Master Port 0 (ARM7 core) is present with burst enabled

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Master Port 1 (DMA) is present with burst disabled

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Slave Port 0 (Flash) is present

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Slave Port 1 (FlexBus) is present

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Slave Port 3 (SRAM) is present

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Slave Port 5 (BAM) is present

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Slave Port 7 (AIPS) is present

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32-bit datapath

15.1.4

Modes of Operation

The crossbar switch bus provides two arbitration modes, fixed or round-robin. The arbitration mode may

be set on a slave by slave basis. For slaves configured for fixed arbitration mode, a unique arbitration level

is assigned to each bus master.

For a given slave with fixed arbitration operation, the highest priority active master accessing that slave is

granted the master bus switch path to that slave. A higher priority master will block access to a given slave

from a lower priority master as long as the higher priority master continuously requests that slave.

For a given slave with round-robin arbitration, active masters accessing that slave are initially granted the

slave based on their master port number. Master priority is then modified in a wrap-around manner to give

all masters fair access to the slave.

15.2

External Signal Description

There are no AXBS signals that drive or are driven from MCU pins.

15.3

Memory Map Definition

There are two registers that reside in each slave port of the crossbar switch bus. Read and write transfers

both require two IP bus clock cycles. The registers can only be read from and written to in supervisor

mode. Additionally, these registers can only be read from or written to by 32-bit accesses. Non 32-bit

accesses to legal registers are ignored.

Table 15-2. MAC72xx AXBS Master and Slave Ports

Master Port

Slave Port

M0: ARM7 Core

S0: Selectable

M1: eDMA

S1: Selectable

S3: SRAM Controller

S5: Boot Assist Module (BAM)

S7: Peripheral Bus Bridge (AIPS)

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