MAC7200 datasheet(389/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

311

this value to “maximum – 1" in the wakeup logic. This guarantees that a level 15 interrupt request

generates the sleep mode exit.

14.10.3 Interrupt Service Routines

This section focuses on the interaction of the interrupt masking functionality with the service routine.

Figure 14-13 presents a timing diagram showing various phases during the execution of an interrupt

service routine with the controller level masking functionality enabled. It is important to note the time scale

in this diagram is not meant to be accurate.

Figure 14-13. Interrupt Service Routine and Masking (Not To Scale)

Consider the events depicted in each “segment” [A-G] of this diagram.

In A, an interrupt request is asserted, which is mapped into the FIQ core signal.

As B begins, the interrupt request is recognized and the core begins FIQ exception processing. During the

core’s exception processing, the CPSR sets the F bit, disabling all interrupts. At the end of the core’s

exception processing, control passes to the interrupt service routine, shown as the beginning of segment C.

During C, the ISR performs the interrupt acknowledge read cycle to retrieve the vector number associated

with the request. As the interrupt acknowledge read is performed, the vector number is returned to the core,

and the CLMASK register raised to level n, the interrupt level being acknowledged. The former contents

of the CLMASK is loaded into the SLMASK register at this time, at the end of C.

During segment D, the ISR accesses the peripheral to negate the interrupt request source. At the conclusion

of segment D, the CPSR[F] flag is cleared to re-enable interrupts.

ipi_int

CORE

CPSR[F]

CLMASK

SLMASK

Interrupts

Enabled

Disabled

-1

fiq xcpt

iack

-1

Enabled

Disabled

Interrupt Service Routine

iack

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