MAC7200 datasheet(395/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

317

The Priority Register can only be accessed with 32-bit accesses. Once the RO (Read Only) bit has been set

in the slave Control Register the Priority Register can only be read, attempts to write to it will have no

effect on the PR and result in a bus error response.

Additionally, no two available master ports may be programmed with the same priority level. Attempts to

program two or more available masters with the same priority level will result in an error response and the

PR will not be updated.

15.4.2

Control Register

The Control Register (CR) controls several features of each slave port.

The Read Only (RO) bit will prevent any registers associated with this slave port from being written to

once set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only

a reset condition will allow it to be written again.

The Halt Low Priority (HLP) bit will set the priority of a request to enter low power mode to the lowest

possible priority for initial arbitration of the slave ports. By default it is the highest priority. Please note,

setting this bit will not effect the request for low power mode from attaining highest priority once it has

control of the slave ports.

The Arbitration Mde (ARB) bits control the arbitration mode. The arbitration mode may be fixed or

round-robin.

The Parking Control (PCTL) bits determine how the slave port will park when no master is actively

making a request. The available options are to park on the master defined by the PARK bits, park on the

last master to use the slave port, or go into a low power park mode which will force all the outputs of the

Name

Reserved

DMA

Core

Type

rrr

Reset

000

010

000

Table 15-5. Priority Register Descriptions

Field

Description

31–5

Priority Register Reserved. These bits are reserved for future expansion. They read as zeros and should be written

with zeros for upward compatibility.

DMA_

MSTR

DMA Master Priority. This bit sets the arbitration priority for this port on the associated slave port.

This bit is initialized by hardware reset. The reset value is 1.

0 This master has the highest priority when accessing the slave port.

1 This master has the lowest priority when accessing the slave port.

3–1

Priority Register Reserved.These bits are reserved for future expansion. They read as zeros and should be written

with zeros for upward compatibility.

CORE_

MSTR

Core Master Priority. This bit sets the arbitration priority for this port on the associated slave port.

This bit is initialized by hardware reset. The reset value is 0

0 This master has the highest priority when accessing the slave port.

1 This master has the lowest priority when accessing the slave port.

Table 15-4. Priority Register Summary (Continued)

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