MAC7200 datasheet(370/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

292

Freescale Semiconductor

processor status register (SPSR_fiq). Finally, a unique fast interrupt stack pointer, contained in R13_fiq,

is activated and the core completes the exception processing by setting bits in the CPSR to disable both

FIQ and IRQ interrupts, and then fetching the instruction at address 0x0000_001c. The processor

continues execution in the FIQ mode, as indicated by the low-order 5 bits (the mode field) of the CPSR.

While executing in this mode, banked copies of five additional general purpose registers

(R[8,9,10,11,12]_fiq) are also available. The shadow copies of these registers are intended to minimize the

need to save/restore the machine register state in memory using the fast interrupt stack pointer.

IRQ processing is similar with the following differences: in IRQ mode, shadow copies of only three

registers are active: R13_irq (the interrupt request stack pointer), R14_irq (the PC of the interrupted

instruction) and the SPSR_irq (the saved processor status register). The CPSR is configured to disable only

IRQ interrupts, and the processor completes exception processing by fetching the instruction at address

0x0000_0018.

For all ARM processors, the processing of any exception forces exit from Thumb mode (if enabled), and

the address loaded into the R14_{fiq,irq} link register is actually the program counter of the interrupted

instruction plus 4. Thus, this instruction address must be adjusted before returning to the interrupted

instruction at the completion of the service routine.

A summary of the operations associated with interrupt exception processing is shown in Figure 14-4:

14.8

Memory Map/Register Definition

The register programming model for the interrupt controller is memory-mapped to a 256-byte space within

the addresses serviced by the IPS controller. In the following discussion, there are a number of

program-visible registers greater than 32 bits in size. For these control fields, the physical register is

partitioned into two 32-bit values: a register “high” (the upper word) and a register “low” (the lower word).

The nomenclature <reg_name>H and <reg_name>L is used to reference these values.

Table 14-4. ARM Interrupt Exception Summary

FIQ

IRQ

Interrupt Sample

Detect FIQ asserted

Detect FIQ negated,

IRQ asserted

Link Register

R14_fiq = nextInst + 4

R14_irq = nextInst + 4

Saved Status Register

SPSR_fiq = CPSR

SPSR_irq = CPSR

Current Processor

Status Register

CPSR[M] = 5’b10001,

CPSR[T] = 1’b0,

CPSR[F] = 1’b1,

CPSR[I] = 1’b1

CPSR[M] = 5’b10010,

CPSR[T] = 1’b0,

CPSR[F] = unaffected,

CPSR[I] = 1’b1

Stack Pointer

Activate R13_fiq

Activate R13_irq

Other Banked Registers

Activate R[8-12]_fiq

None

Program Counter

= 0x0000_001c

= 0x0000_0018

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