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MAC7200 Datasheet(PDF) 360 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 360 Page - Freescale Semiconductor, Inc |
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360 / 976 page  MCM as Implemented on MAC7200 MAC7200 Microcontroller Family Reference Manual, Rev. 2 282 Freescale Semiconductor For the MAC7200 family of devices, only certain crossbar switch re-mappings are valid. The reset value of the register depends on the Chip Mode selected and the security state of the device, and is discussed in detail in Chapter 9, “Device Memory Map”. After reset, the AAMR register may be re-programmed to change the memory map of the system as follows: NOTE The SRAM is fixed at address $4000 0000, and may be re-mapped to either $0000 0000 or $2000 0000. When this is done, the SRAM will appear at both addresses in the memory map. Consult the MCM Block Guide for further information about configuring and using the MCM. 13.3.2 MCM Features The MCM module is an on-platform IPI module that implements several varied SoC level features, including the following: 13.3.2.1 Processor Core Type (PCT) This 16-bit register identifies the revision ID of the platform/core pair, as follows: Table 13-38. AAMR Register Configurability 1 1. Not all re-mappings may be available in all Chip Modes/Security states. Please refer to Chapter 9, “Device Memory Map for more details on valid memory map configurations. AAMR Bits Base Address Allowed Values 31:28 $E000 0000 $f (Peripheral Space) 27:24 $C000 0000 $0 (Unused) 23:20 $A000 0000 $d (BAM) 19:16 $8000 0000 $0 (Unused) 15:12 $6000 0000 $0 (Unused) 11:8 $4000 0000 $b (SRAM) 7:4 $2000 0000 $8 (Program Flash), $9 (External Bus), $b (SRAM) 3:0 $0000 0000 $8 (Program Flash), $9 (External Bus), $b (SRAM) Table 13-39. Processor Core Type (PCT) Values Core PCT Comment ARM7 $A700 Value for the MAC72xx ARM9 $A900 ARM11 $A110 ColdFire v2 $CF20 ColdFire v3 $CF30 |
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