MAC7200 datasheet(341/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

263

13.2.2.15 ECC Registers

For designs including error-correcting code (ECC) implementations to improve the quality and reliability

of memories, there are a number of program-visible registers for the sole purpose of reporting and logging

of memory failures. These optional registers include:

•

ECC Configuration Register (ECR)

•

ECC Status Register (ESR)

•

ECC Error Generation Register (EEGR)

•

Flash ECC Address Register (FEAR)

•

Flash ECC Master Number Register (FEMR)

•

Flash ECC Attributes Register (FEAT)

•

Flash ECC Data Register (FEDR)

•

RAM ECC Address Register (REAR)

•

RAM ECC Syndrome Register (RESR)

•

RAM ECC Master Number Register (REMR)

•

RAM ECC Attributes Register (REAT)

•

RAM ECC Data Register (REDR)

The details on the ECC registers are provided in the subsequent sections. If the design does not include

ECC on the memories, these addresses are reserved locations within the MCM’s programming model.

13.2.2.15.1

ECC Configuration Register (ECR)

The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors

are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access

to be terminated with an error condition. In many cases, this error termination is reported directly by the

initiating bus master. However, there are certain situations where the occurrence of this type of

non-correctable error is not reported by the master. Examples include speculative instruction fetches which

are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting logic in

the MCM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In

addition to the interrupt generation, the MCM captures specific information (memory address, attributes

and data, bus master number, etc.) which may be useful for subsequent failure analysis.

The reporting of single-bit memory corrections can only be enabled via a an SoC-configurable module

input signal. While not directly accessible to a user, this capability is viewed as important for error logging

and failure analysis.

See Figure 13-23 and Table 13-20 for the ECC Configuration Register definition.

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