MAC7200 datasheet(338/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

260

Freescale Semiconductor

13.2.2.14.5

Peripheral Power Management Register (PPMR{H,L})

The PPMR{H,L} registers provide a bit map for controlling the generation of the module clocks for each

decoded address space associated with the AIPS controller. Each AIPS controller decodes the mapped

address space into sixty-four 16 KByte “slots” (32 on-platform and 32 off-platform) plus a 63 MByte

off-platform global region. The PPMR provides a unique control bit for each of these address spaces that

defines whether the module clock for the given space is enabled or disabled. It is software’s responsibility

to appropriately disable module clocks using the PPMR only when a module is completely unused or

quiescent.

Since the operation of the crossbar switch, the AIPS controller and the Miscellaneous Control Module

(MCM) are fundamental to the operation of the core platform, the clocks for these three modules cannot

be disabled.

The individual bits of the PPMR can be modified using a read-modify-write to this register directly or

indirectly through writes to the PPMRS and PPMRC registers to set/clear individual bits. If the static

module enable is negated, the appropriate PPMR bit is automatically set by MCM after the negation of the

platform reset and cannot be altered by any subsequent IPS writes.

See Figure 13-19, Figure 13-20, and Figure 13-18 for the PPMR definition.

Table 13-17. Peripheral Power Management Clear 1 (PPMRC1) Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

PPMRC1[6:0]

Clear Module Clock Disable.

0-63

Clear corresponding bit in PPMR1{H,L}, enabling the module clock.

64-127 Clear all bits in PPMR1{H,L}, enabling all the module clocks.

CD63 CD62 CD61 CD60 CD59 CD58 CD57 CD56 CD55 CD54 CD53 CD52 CD51 CD50 CD49 CD48

Reset

000000000000000

9876543210

CD47 CD46 CD45 CD44 CD43 CD42 CD41 CD40 CD39 CD38 CD37 CD36 CD35 CD34 CD33 CD32

Reset

000000000000000

Figure 13-19. Peripheral Power Management Register High (PPMRH)

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