MAC7200 datasheet(337/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

259

13.2.2.14.3

Peripheral Power Management Set Register 1 (PPMRS1)

The PPMRS1 register provides a simple memory-mapped mechanism to set a given bit in the

PPMR1{H,L} registers to disable the clock for a given IPS module without the need to perform a

read-modify-write on the PPMR1. The data value on a register write causes the corresponding bit in the

PPMR1{H,L} register to be set. A data value of 64 to 127 provides a global set function, forcing the entire

contents of the PPMR1{H,L} to be set, disabling all IPS module clocks. Reads of this register return all

zeroes. See Figure 13-17 and Figure 13-16 for the PPMRS1 definition.

13.2.2.14.4

Peripheral Power Management Clear Register 1 (PPMRC1)

The PPMRC1 register provides a simple memory-mapped mechanism to clear a given bit in the

PPMR1{H,L} registers to enable the clock for a given IPS module without the need to perform a

read-modify-write on the PPMR1. The data value on a register write causes the corresponding bit in the

PPMR1{H,L} register to be cleared. A data value of 64 to 127 provides a global clear function, forcing the

entire contents of the PPMR1{H,L} to be zeroed, enabling all IPS module clocks. In the event on

simultaneous writes to the PPMRS1 and PPMRC1, the write to the PPMRC1 takes priority. Reads of this

65432

0000

PPMRS1[6:0]

Reset

—

0000

Figure 13-17. Peripheral Power Management Set 1 (PPMRS1) Register

Table 13-16. Peripheral Power Management Set 1 (PPMRS1) Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

PPMRS1[6:0]

Set Module Clock Disable.

0-63

Set corresponding bit in PPMR1{H,L}, disabling the module clock.

64-127 Set all bits in PPMR1{H,L}, disabling all the module clocks.

65432

0000

PPMRC1[6:0]

Reset

—

0000

Figure 13-18. Peripheral Power Management Clear 1 (PPMRC1) Register

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