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MAC7200 Datasheet(PDF) 403 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 403 Page - Freescale Semiconductor, Inc |
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403 / 976 page  AIPS Protocol MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 325 Figure 16-2. AIPS Memory Map The AIPS is responsible for indicating to IPS peripherals if an access is in supervisor or user mode. The AIPS may block user mode accesses to certain IPS peripherals or it may allow the individual IPS peripherals to determine if user mode accesses are allowed. In addition, peripherals may be designated as write-protected. The AIPS supports the notion of “trusted” masters for security purposes. Masters may be individually designated as trusted for reads, trusted for writes, or trusted for both reads and writes, as well as being forced to look as though all accesses from a master are in user-mode privilege level. Refer to Section 16.4.2, “Control Registers,” for more information. All peripheral devices require aligned accesses equal to or smaller in size than the peripheral size. An exception to this rule is supported for 32-bit peripherals to allow memory to be placed on the IPS. 16.2 AIPS Protocol 16.2.1 8/16/32--bit accesses The following table defines the byte ordering scheme on the IPI bus in the MAC72xx. AIPS (SPP Module 0) 0x0000 SPP Module 1 0x0000 0x0000 0x0000 0x0007 0x0007 IPS Module 0 0x0008 IPS Module 1 0x0008 IPS Module 2 0x0008 IPS Module 3 0x0008 IPS Module 31 0x000F IPS Global Module 0 IPS Global Module 1 0x01FF 0x03FF • • • • • • SPP Module 2 SPP Module 3 SPP Module 30 SPP Module 31 • • • • • • 0000 4000 8000 C000 8000 C000 0000 4000 8000 C000 C000 0000 0000 – – – – – – – – – – – – – 3FFF 7FFF BFFF FFFF BFFF FFFF 3FFF 7FFF BFFF FFFF FFFF FFFF FFFF 0x0000 0x0000 0x0000 0x0000 0x0007 0x0007 0x0008 0x0008 0x0008 0x0008 0x000F 0x0010 0x0200 |
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