MAC7200 datasheet(401/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

323

Chapter 16

AHB to IPI Bridge (AIPS)

16.1

Introduction

The AIPS provides the interface between the 32-bit system bus (AHB-Lite 2.v6) and the 32-bit peripheral

bus. The AIPS can support up to 32 peripherals, and implements various levels of protection for each

peripheral, including a trusted master scheme for both the ARM7 core (MASTER0) and the eDMA

(MASTER1).

Not all peripherals are present on all devices. It is the responsibility of the application to ensure that no

accesses to reserved address ranges are performed.

16.1.1

Features

The following list summarizes the key features of the AIPS:

•

Support for AHB v2.0 AHB-Lite bus protocol

•

32-bit address bus width

•

32-bit data bus width

•

2 clocks for READs, 3 clocks for WRITEs

•

32 on-platform peripheral module enables

•

32 off-platform peripheral module enables (+ one bit-wise OR signal)

•

2 global off-platform address space module enables

•

Supervisor/User/Test access support

•

Software enabled write buffering (posted write)

•

Memory Map: 64MByte (ADDR[25:0]), byte addressable

— 512KByte: Platform Peripherals #0-#31 (32 modules x 16KBytes each)

– $0000_0000 - $0007_FFFF

— 512KByte: MAC72xx Peripherals (32 peripherals x 16KBytes each)

– $0008_0000 - $00F_FFFF

— 63MBytes: Global External Address Space

– $0010_0000 - $03FF_FFFF

•

The AIPS is not relocatable under any circumstances

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