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MAC7200 Datasheet(PDF) 404 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 404 Page - Freescale Semiconductor, Inc |
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404 / 976 page ![]() AIPS Protocol MAC7200 Microcontroller Family Reference Manual, Rev. 2 326 Freescale Semiconductor Essentially, this is a “big endian like” bus, in the sense that high-order bits are stored at the lowest address. 32-bit register Implement one 32-bit register REG1 with base address $00. Figure xx: Register #1 Description (REG1) Performing a READ operation will return the following data: Table 16-1. AIPS 32-bit byte lanes ips_addr[1:0] data[31:24] data[23:16] data[15:8] data[7:0] 00 X 01 X 10 X 11 X 00 X X 01 ERR ERR ERR ERR 10 X X 11 ERR ERR ERR ERR 00 XXXX 01 ERR ERR ERR ERR 10 ERR ERR ERR ERR 11 ERR ERR ERR ERR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R REG1[31:16] W RESET: 15 14 13 12 11 10 9876543210 RREG1[15:0] W RESET: = Unimplemented or Reserved Register address: Base + $00 |
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