MAC7200 datasheet(408/976 Pages) FREESCALE

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Memory Map/Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

330

Freescale Semiconductor

16.4.1

Overview

There are eleven registers that control the AIPS. All registers are 32-bit registers and can only be accessed

in supervisor mode by trusted bus masters. Additionally, these registers must only be read from or written

to by a 32-bit aligned access. AIPS registers are mapped into the PACR0 address space.

Two system clocks are required for read accesses and three system clocks are required for write accesses

to the AIPS registers.

16.4.2

Control Registers

The memory map for the AIPS program-visible registers is shown in Table 16-2. The MPROT fields of

the MPR and the PACR and OPACR registers are 4 bits in width.

For the MAC7200, the processor complex is master zero and the enhanced direct memory access module

is master one. The mapping between access control registers and peripheral modules is shown in the

following table. Note that not all peripherals can be accessed in all MAC7200 operational modes.

Table 16-2. AIPS Register Memory Map

AIPS Offset

[31:28]

[27:24]

[23:20]

[19:16]

[15:12]

[11:8]

[7:4]

[3:0]

0x0000

MPROT0

MPROT1

RFU

0x0004

RFU

0x0020

PACR0

PACR1

PACR2

RFU

0x0024

RFU

0x0028

PACR16

PACR17

PACR18

RFU

0x002c

RFU

0x0040

OPACR0

OPACR1

OPACR2

OPACR3

RFU

OPACR5

OPACR6

RFU

0x0044

RFU

OPACR11

RFU

OPACR13

OPACR14

OPACR15

0x0048

RFU

OPACR17

OPACR18

RFU

OPACR23

0x004c

OPACR24

RFU

OPACR26

RFU

OPACR28

RFU

0x0050

Reserved

Table 16-3. MAC7200 Peripheral to Access Control Register Map

Address Range

Module

Access Control Register

0xFC00_0000 – 0xFC00_3FFF

AIPS – AMBA to IP Bus Bridge

PACR0

0xFC00_4000 – 0xFC00_7FFF

AXBS – AMBA Crossbar Switch

PACR1

0xFC00_8000 – 0xFC00_BFFF

FlexBus – External Interface Module

PACR2

0xFC00_C000 – 0xFC03_FFFF

RFU

0xFC04_0000 – 0xFC04_3FFF

MCM – Miscellaneous Control Module

PACR16

0xFC04_4000 – 0xFC04_7FFF

eDMA – Enhanced Direct Memory Access Controller

PACR17

0xFC04_8000 – 0xFC04_BFFF

INTC – Interrupt Controller

PACR18

0xFC04_C000 – 0xFC07_FFFF

RFU

0xFC08_0000 – 0xFC08_3FFF

SSM – System Service Module

OPACR0

0xFC08_4000 – 0xFC08_7FFF

DMA Mux – Direct Memory Access Controller Mux

OPACR1

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