MAC7200 datasheet(412/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

334

Freescale Semiconductor

16.5.1.2

Registers

Any attempt to access registers or register bitfields which are not present in the final instantiation will

result in a read returning zeroed data and writes being ignored.

16.5.2

Access Protections

The AIPS provides programmable access protections for both masters and peripherals. It allows the

privilege level of a master to be overridden, forcing it to user-mode privilege, and allows masters to be

designated as trusted or untrusted. Peripherals may require supervisor privilege level for access, may

restrict access to a trusted master only, and may be write-protected.

This functionality is described in Section 16.4.3.1, “Master Privilege Registers (MPROT),”

Section 16.4.3.2, “Peripheral Access Control Registers (PACR),” and Section 16.4.3.3, “Off-Platform

Peripheral Access Control Registers (OPACRs).”

16.5.3

Access Support

Aligned word and halfword accesses, as well as byte accesses are supported for 32-bit peripherals.

Peripheral registers must not be misaligned, although no explicit checking is performed by the AIPS.

16.5.4

Read Cycles

Two clock read accesses are possible to on-platform peripherals with the AIPS when the requested access

size is 32-bits or smaller.

16.5.5

Write Cycles

Three clock write accesses are possible to on-platform peripherals with the AIPS when the requested

access size is 32-bits or smaller.

16.5.6

Aborted Cycles

The AIPS follows a standard procedure when a system bus cycle is aborted and the abort is initiated by the

AIPS itself or the targeted IP bus peripheral. The AIPS either blocks initiation or immediately terminates

any IP bus activity that is ongoing.

There are several conditions that can cause the AIPS to abort the current operation and report an error. The

first is the case in which the targeted IP bus peripheral asserts a bus error. In this case the AIPS immediately

terminates access to the targeted IP bus peripheral and follows the abort procedure described above.

Whether the current IP bus access is a multi-cycle access or a single cycle access has no bearing on the

behavior of the AIPS. The AIPS responds identically in both cases.

The second case that can cause an error response to the AHB is when an access is attempted to an IP bus

peripheral whose corresponding PACR or OPACR settings do not allow the access, thus causing a

permissions violation. In this case the AIPS does not initiate any IP bus activity, but instead responds by

following the abort procedure described above.

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