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MAC7200 Datasheet(PDF) 413 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 413 Page - Freescale Semiconductor, Inc

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Initialization/Application Information
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
335
The third case that can cause an error response to the AHB is when an access is attempted to a location at
which there is no IP bus peripheral. In this case the AIPS does not initiate any IP bus activity but instead
responds by following the same abort procedure described above for a permissions violation.
16.6
Initialization/Application Information
The AIPS is configured at reset with all masters trusted for both reads and writes, all masters using their
supervisor access attribute, and all peripherals supervisor protected. After reset, a bus master may be used
to change the Master Privilege Registers (MPRs), the Peripheral Access Control registers (PACRs), and
the Off-platform Peripheral Access Control registers (OPACRs) as needed as described in Section 16.4.2,
“Control Registers.”
16.7
AIPS Bus Aborts
16.7.1
IPI Register Interface
The AIPS module supports Peripheral Bus bus aborts, and enforces the following memory map:
Address aborting in the AIPS is done only on a 32-bit address boundary.
Supervisor Access: All accesses to the AIPS registers must be in Supervisor Mode. All User Mode
accesses are aborted.
16.7.2
IPI Bridge Interface
In addition to the IPI interface, the AIPS can abort transfers through the bridge itself. The following
transfers will be aborted:
— User mode access to any AIPS slave with the corresponding SP bit set in the PACR/OPACR
register.
— Write to any AIPS slave with the corresponding WP bit set in the PACR/OPACR register.
— Any access from an untrusted master to any AIPS slave with the corresponding TP bit set in
the PACR/OPACR register.
— Any access to an AIPS slave that is not implemented (i.e.-marked as “Reserved” in the
documentation)
(See Section 9.9, “Peripheral Bus Memory Map” for a list of PACR/OPACR registers)
Table 16-6. AIPS Bus Aborts
Abort
Allowed
$0000-$0007
$0008-$001f
$0020-$002f
$0030-$003f
$0040-$0057
$0058-$3fff



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