MAC7200 datasheet(417/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

339

Chapter 17

External Bus Interface (FlexBus)

17.1

Introduction

This chapter describes data transfer operations, error conditions, and reset operations. It describes transfers

initiated by the MAC7200 and includes detailed timing diagrams showing the interaction of signals in

supported bus operations.

NOTE

Unless otherwise noted, in this chapter “clock” refers to the CLKOUT used

for the bus.

The external bus interface on the MAC7200 can be used as a bus interface to external peripherals or

memories. In general, the external bus is available on larger pin count packages only, which also makes it

ideal for debugging purposes. It is a simple, flexible bus that supports a variety of external memory devices

with little or no external logic needed, and is based on the external bus of the 68000/Coldfire family of

devices. All transfers on the external bus are controlled by the MCU masters (CPU or eDMA) only (i.e.,

the MAC7200 device may not be used as an external bus slave).

The interface is implemented with a 16-bit data bus capable of supporting byte, half word (2 byte) and

word (4 byte) transfers.

Accesses which are greater than the selected port width of the data bus (i.e.,16-bit access with an 8-bit Port

Size) are automatically decomposed into a sequence of individual transfers. The address bus has up to 22

address lines (ADDR0[0:21]), allowing access to up to 4Mbytes of external addresses.

Three chip select signals (CS[0:2]) can be configured for different address ranges and transfers types,

including Auto Acknowledge with a defined number of wait states. If an access to the external bus maps

to no chip selects, the FlexBus will return a bus abort. Accesses that map to multiple chip selects will cause

multiple chip selects to be asserted. It is the responsibility of the external hardware to correctly handle this

situation, especially in the case of a read.

Chip select CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word

(16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash

memories.

The port width of the data bus can be selected as either 8-bits or 16-bits wide. The value of Port F3 on reset

is used to determine the external data bus port width, as described in Section 2.2, “MCU Hardware

Configuration Summary” and Table 17-2.

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