MAC7200 datasheet(421/976 Pages) FREESCALE

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Chip-Select Operation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

343

17.2.8

Transfer Acknowledge (TA)

This signal indicates that the external data transfer is complete. During a read cycle, when the processor

recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the

processor recognizes TA, the bus cycle is terminated.

If auto-acknowledge is disabled, the external device drives TA to terminate the bus transfer; if

auto-acknowledge is enabled, the TA is generated internally after a specified wait states or the external

device may assert external TA before the wait-state countdown which in turn terminates the cycle early.

The MAC7200 negates CSn a cycle after the last TA asserts. During read cycles, the peripheral must

continue to drive data until TA is recognized. For write cycles, the processor continues to drive data one

clock after CSn is negated.

The number of wait states is determined either by internally programmed auto acknowledgement or by the

external TA input. If the external TA is used, the peripheral has total control on the number of wait states.

17.3

Chip-Select Operation

Each chip-select has a dedicated set of the following registers for configuration and control.

•

Chip-select address registers (CSARn) control the base address space of the chip-select.

Section 17.3.2.1, “Chip-Select Address Registers (CSAR0–CSAR2).

•

Chip-select mask registers (CSMRn) provide 16-bit address masking and access control.

Section 17.3.2.2, “Chip-Select Mask Registers (CSMR0–CSMR2).

•

Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state

generation, address setup and hold times, and automatic acknowledge generation features.

Section 17.3.2.3, “Chip-Select Control Registers (CSCR0–CSCR2).

CS0 is a global chip-select after reset and provides re-locatable boot ROM capability.

17.3.1

General Chip-Select Operation

When a bus cycle is initiated, the MAC7200 first compares its address with the base address and mask

configurations programmed for chip-selects 0–2 (configured in CSCR0–CSCR2). If the driven address

matches a programmed chip-select, the appropriate chip-select is asserted fulfilling the requirements as

programmed in the respective configuration register.

17.3.1.1

8-bit and 16-bit Port Sizing

Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 17.3.2.3,

“Chip-Select Control Registers (CSCR0–CSCR2).” Note that the MAC7200 always drives a 22-bit

address on the address bus in the first cycle regardless of the external device’s address size. The external

device must connect its address lines to the appropriate ADDR bits starting from ADDR0 and upward. It

must also connect its data lines to the DATA bus starting from the DATA15 and downward. No bit ordering

is required when connecting address and data lines to the bus. For example, a 16-bit address/16-bit data

device would connect its addr[15:0] to ADDR[15:0] and data[15:0] to DATA[15:0]. See Figure 17-5 for

graphical connection.

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