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Chip-Select Operation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

344

Freescale Semiconductor

17.3.1.2

Global Chip-Select Operation

CS0, the global (boot) chip-select, allows address decoding for boot ROM before system initialization. Its

operation differs from other external chip-select outputs after system reset.

After system reset, CS0 is asserted for every external access. No other chip-select can be used until the

valid bit, CSMR0[V], is set, at which point CS0 functions as configured. After this, CS[2:1] can be used

as well. At reset, the port size, and automatic acknowledge functions of the global chip-select are

determined by the logic levels on the PF[3:2] signals (see Table 17-1 and Table 17-2).

17.3.2

Chip-Select Registers

The following tables describe in detail the registers and bit meanings for configuring chip-select operation.

The chip-select controller register map is accessed relative to the memory base address register (MBAR).

Table 17-4 shows the chip-select register memory map. Reading unused or reserved locations terminates

normally and returns zeros.

Table 17-4. Chip-Select Registers

Offset

[31:24]

[23:16]

[15:8]

[7:0]

ResetValue

Access 1

1. The access column indicates whether the corresponding register allows both read/write functionality (R/W), read-only

functionality (R), or write-only functionality (W). A read access to a write-only register returns zeros. A write access

to a read-only register has no effect.

0x00

Chip-select address

Reserved 2

2. Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these

reserved address spaces and reserved register bits have no effect.

0x0000_0000

R/W

0x04

Chip-select mask register—bank 0 (CSMR0)

0x0000_0000

R/W

0x08

Chip-select control register—bank 0 (CSCR0)

BSTW = 0

BSTR = 0

PS = AD[1:0]

AA = AD[2]

WS = 111111

WRAH = 11

RDAH = 11

ASET = 11

SWSEN = 0

SWS = 000000

R/W

0x0C

Chip-select address

Reserved 2

0x0000_0000

R/W

0x10

Chip-select mask register—bank 1 (CSMR1)

0x0000_0000

R/W

0x14

Chip-select control register—bank 1 (CSCR1)

0x0000_0000

R/W

0x18

Chip-select address

Reserved 2

0x0000_0000

R/W

0x1C

Chip-select mask register—bank 2 (CSMR2)

0x0000_0000

R/W

0x20

Chip-select control register—bank 2 (CSCR2)

0x0000_0000

R/W

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