MAC7200 datasheet(426/976 Pages) FREESCALE

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Chip-Select Operation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

348

Freescale Semiconductor

21–20

ASET

Address setup. This field controls the asserting of chip-select with respect to assertion of

a valid address and attributes.

00 Assert chip-select on rising clock edge after address is asserted. (Default CSn)

01 Assert chip-select on second rising clock edge after address is asserted.

10 Assert chip-select on third rising clock edge after address is asserted.

11 Assert chip-select on fourth rising clock edge after address is asserted.(Reset CS0)

19–18

RDAH

Read Address Hold or (Deselect). This field controls the address and attribute hold time

after the termination during a read cycle that hits in the chip-select address space.

00 Hold address and attributes one cycle after CSn negates on reads. (Default CSn)

01 Hold address and attributes two cycles after CSn negates on reads.

10 Hold address and attributes three cycles after CSn negates on reads.

11 Hold address and attributes four cycles after CSn negates on reads. (Reset CS0)

17–16

WRAH

Write Address Hold or (Deselect). This field controls the address, data and attribute hold

time after the termination of a write cycle that hits in the chip-select address space.The

hold time only applies at the end of a transfer. Therefore, a burst transfer which is burst

inhibited only has a hold time added after the last bus cycle.]

00 Hold address and attributes one cycle after CSn negates on writes. (Default CSn)

01 Hold address and attributes two cycles after CSn negates on writes.

10 Hold address and attributes three cycles after CSn negates on writes.

11 Hold address and attributes four cycles after CSn negates on writes. (Reset CS0)

15–10

Wait states. The number of wait states inserted after CSn asserts and before an internal

transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63

wait states). If AA = 0, TA must be asserted by the external system regardless of the

number of wait states generated. In that case, the external transfer acknowledge ends the

cycle. An external TA supersedes the generation of an internal TA.

—

Reserved, should be cleared.

Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge

for accesses specified by the chip-select address.

0No internal TA is asserted. Cycle is terminated externally.

Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn

and the external system asserts an external TA before the wait-state countdown

asserts the internal TA, the cycle is terminated. Burst cycles increment the address bus

between each internal termination.

7–6

Port size. Specifies the width of the data port associated with each chip-select. It

determines where data is driven during write cycles and where data is sampled during read

cycles.

00 32-bit port size. Valid data sampled and driven on D[31:0]. Not valid on MAC72xx.

01 8-bit port size. Valid data sampled and driven on D[7:0]

1x 16-bit port size. Valid data sampled and driven on D[15:0]

—

Reserved, should be cleared.

BSTR

Burst read enable. Specifies whether burst reads are used for memory associated with

each CSn.

Data exceeding the specified port size is broken into individual, port-sized non-burst

reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.

Enables data burst reads when the transfer size is larger than the specified port size,

including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line

reads from 8- and 16-bit ports.

Table 17-7. CSCRn Field Descriptions (Continued)

Bits

Name

Description

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