MAC7200 datasheet(428/976 Pages) FREESCALE

428 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

350

Freescale Semiconductor

Figure 17-5. Connections for External Memory Port Sizes

17.4.3

Bus Cycle Execution

Basic bus operations occur in four clocks, as follows:

1. At the first clock edge, the address, and attributes are driven.

2. CSn is asserted at the second rising clock edge to indicate which device has been selected and by

that time the address and attributes are valid and stable. is negated at this edge.

For a write transfer, data is driven on the bus at this clock edge and continues to be driven until one

clock cycle after CSn negates. For a read transfer, data is also returned at this cycle.

External slave asserts TA at this clock edge.

3. Read data and TA are sampled on the third clock edge. TA can be negated after this edge and read

data can then be tristated.

4. CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be

an idle clock between cycles to provide hold time for address, attributes, and write data.

17.4.3.1

Data Transfer Cycle States

The data transfer operation in the MAC7200 is controlled by an on-chip state machine. The state transition

diagram for basic read and write cycles is shown in Figure 17-6.

MAC72xx

DATA[15:8]

DATA[7:0]

External Data Bus

Byte Lanes

Byte 0 (MSB)

Byte 1

Byte 2

Byte 3 (LSB)

16-Bit Port Memory

Byte 0 (MSB)

Byte 1

Byte 2

Byte 3 (LSB)

8-Bit Port Memory

Byte Select

BWE0

BWE1

MAC7200 Datasheet(PDF) 428 Page - Freescale Semiconductor, Inc