MAC7200 datasheet(427/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

349

17.4

Functional Description

17.4.1

Data Transfer Operation

Data transfers between the MAC7200 and other devices involve the following signals:

•

Address / data bus (ADDR[21:0] / DATA[15:0])

•

Control signal TA

•CSn

•

BWE[1:0]

•

Attribute signals (R/W, TBST)

The address and write data (ADDR[21:0] and DATA[15:0]), R/W, CSn, and all attribute signals change on

the rising edge of the clock. Read data is registered in the MAC7200 on the rising edge of the clock.

The MAC7200 FlexBus supports byte, word, longword, and 16-byte cache line operand transfers and

allows accesses to 8- and 16-bit data ports. Transfer parameters such as address setup and hold, port size,

the number of wait states for the external device being accessed, automatic internal transfer termination

enable or disable, and burst enable or disable are programmed in the chip-select control registers (CSCRs),

Section 17.3.2.3, “Chip-Select Control Registers (CSCR0–CSCR2).

17.4.2

Data Byte Alignment and Physical Connections

The MAC7200 aligns data transfers in FlexBus byte lanes, the number of lanes depending on the width of

the data port. Figure 17-5 shows the byte lanes that external memory should be connected to and the

sequential transfers if a longword is transferred for two port sizes. For example, an 8-bit memory should

be connected to the single lane DATA[7:0]. A longword transfer through this 8-bit port takes four transfers

on DATA[7:0], starting with the MSB and going to the LSB. A longword transfer through a 16-bit port

requires two transfers on each of the two byte lanes of the FlexBus.

BSTW

Burst write enable. Specifies whether burst writes are used for memory associated with

each CSn.

Break data larger than the specified port size into individual port-sized, non-burst

writes. For example, a longword write to an 8-bit port takes four byte writes.

Enables burst write of data when the transfer size is larger than the specified port size,

including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes

to 8- and 16--bit ports.

2–0

—

Reserved, should be cleared.

Table 17-7. CSCRn Field Descriptions (Continued)

Bits

Name

Description

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