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MAC7200 Datasheet(PDF) 425 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 425 Page - Freescale Semiconductor, Inc |
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425 / 976 page  Chip-Select Operation MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 347 17.3.2.3 Chip-Select Control Registers (CSCR0–CSCR2) Each CSCRn, Figure 17-3, controls the auto acknowledge, external master support, address setup and hold times, port size, burst capability, and activation of each chip-select. Note that to support the global chip-select, CS0, the CSCR0 reset values differ from the other CSCRs. CS0 allows address decoding for boot ROM before system initialization. Table 17-7 describes CSCRn fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SWS 0 0 SWSEN — ASET RDAH WRAH W Reset: CSCR0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Reset: CSCRs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr MBAR + 0x08 (CSCR0); 0x14 (CSCR1); 0x20 (CSCR2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RWS 0 AA PS 0 BSTR BSTW 0 0 0 W Reset: CSCR0 1 1 1 1 1 1 0 AD2 AD[1:0] 0 0 0 0 0 0 Reset: CSCRs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reg Addr MBAR + 0x08 (CSCR0); 0x14 (CSCR1); 0x20 (CSCR2) Figure 17-4. Chip-Select Control Registers (CSCRn) Table 17-7. CSCRn Field Descriptions Bits Name Description 31–26 SWS Secondary wait states. The number of wait states inserted before an internal transfer acknowledge is generated for burst transfer except for the first termination, which is controlled by the wait state count. The secondary wait state is only used if the secondary wait state enable is set, otherwise the wait state value is used for all burst transfers. 25–24 — Reserved, should be cleared 23 SWSEN Secondary wait state enable. 0 The wait state value is used to insert wait states before an internal transfer acknowledge is generated for all transfers. 1 The secondary wait state value is used to insert wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations. 22 — Reserved, should be cleared |
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