MAC7200 datasheet(429/976 Pages) FREESCALE

429 / 976 page

FlexBus Bus Aborts

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

351

Figure 17-6. Data Transfer State Transition Diagram

Table 17-8 describes the states as they appear in subsequent timing diagrams.

17.5

FlexBus Bus Aborts

17.5.1

IPI Register Interface

The FlexBus module does not support Peripheral Bus aborts, and has the following memory map:

Table 17-8. Bus Cycle States

State

Cycle

Description

All

The read or write cycle is initiated. On the rising clock edge, the MAC7200 places

a valid address on ADDR[21:0]and drives R/W high for a read and low for a write,

if these signals are not already in the appropriate state.

All

On the rising edge of CLK, CSn is asserted. Data is driven on DATA[15:Y] for

writes, and DATA[15:Y] is three-stated for reads. Address continues to be driven

on ADDR[X:0] pins that are unused for data.

If TA is recognized asserted, then the cycle moves on to S2. If TA is not asserted

either internally or externally, then the S1 state continues to repeat.

Read

Data is made available by the external device before the rising edge of CLK with

TA asserted. The MAC7200 will latch data on this rising clock edge.

All

For internal termination the chip select will negate the internal TA signal. For

external termination, the external device should negate TA. Chip select is

negated after the rising edge of CLK at the end of S2.

Read

The external device can stop driving data after the rising edge of CLK at the

beginning of S2. However, data can be driven until the end of S3 or any additional

address hold cycles.

All

Address, data, and R/W go invalid off the rising edge of CLK at the end of S3,

terminating the read or write cycle.

Wait States

Next Cycle

MAC7200 Datasheet(PDF) 429 Page - Freescale Semiconductor, Inc