MAC7200 datasheet(400/976 Pages) FREESCALE

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AXBS Differences from MAC71xx

MAC7200 Microcontroller Family Reference Manual, Rev. 2

322

Freescale Semiconductor

If any part of a read or write falls within an aborted region, the entire transfer is aborted. Since all AXBS

registers are 32-bit, you can not have the situation where an access is partially in an aborted region.

Supervisor Access: All accesses to the AXBS registers must be in Supervisor Mode. All User Mode

accesses are aborted.

NOTE

If the RO bit in a slave port’s Slave General Purpose Control Register is set,

then any write access to that slave’s registers will be aborted.

15.7.2

Master/Slave Interface

In addition to the IPI interface, the AXBS can abort transfers through the crossbar itself. The following

transfers will be aborted:

•

Transfers to an unused slave port, as follows:

— S2: $4000_0000 - $5FFF_FFFF

— S4: $8000_0000 - $9FFF_FFFF

— S6: $C000_0000 - $DFFF_FFFF

•

Writing to a slave address when the RO bit in the slave’s SGPCR register is set (1).

15.8

AXBS Differences from MAC71xx

•

Addition of Slave 5 port (BAM). Note that the BAM code is accessible by the application software.

•

Replaced tightly coupled Flash bus with Slave 0 port. This means that the DMA may also access

the Flash through the same bus as the ARM7 core.

$0f00-$0f04

$0f05-$3fff

Table 15-8. AXBS Bus Aborts (Continued)

Abort

Allowed

MAC7200 Datasheet(PDF) 400 Page - Freescale Semiconductor, Inc