MAC7200 datasheet(472/976 Pages) FREESCALE

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Platform RAM Array Controller (PRAM_CTL)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

394

Freescale Semiconductor

19.2.3.7

ECC Events on Reads

There are two types of ECC events that can occur on a read from the array, a single-bit or a multiple-bit

error. AHB unaligned writes or less than 32-bit writes will generate a read from the array. Therefore, these

transactions are subject to ECC decode events.

19.2.3.7.1

Single Bit Errors

Single-bit errors do not affect the AHB transfer in progress. The data bit in error is logically

complemented or corrected, and the transaction proceeds normally. In addition, the ecc_single_error flag

is asserted during the transfer acknowledge (asserted hready) and the syndrome and related attributes are

valid at this time.

19.2.3.7.2

Mulitiple Bit Errors

A decoded multiple-bit ECC error will result in the termination of the corresponding AHB transaction with

the AHB two cycle ERROR response (hresp). This behavior is shown in Figure 19-9. The first

transaction, a byte write to ’addr y’, results in an error decoded in cycle 2. The data for an errored

transaction is not stored back to the array. The array is left unchanged. The response shown in Figure 19-9

would be the same had the request been a read or unaligned write rather than a less than 32-bit write.

Figure 19-9. Multiple-Bit Error on AHB Read Request

345

addr y

addr z

nonseq

idle

nonseq

byte

word

data y

data z

okay

error

okay

addr y

addr z

2'b01

2'b11

2'b01

data y

data z

hclk

haddr

htrans

hwrite

hsize

hready

hrdata

hresp

ecc_multi_error

pram_addr

pram_we

pram_cs_b

pram_rdata

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