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MAC7200 Datasheet(PDF) 470 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 470 Page - Freescale Semiconductor, Inc |
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470 / 976 page  Platform RAM Array Controller (PRAM_CTL) MAC7200 Microcontroller Family Reference Manual, Rev. 2 392 Freescale Semiconductor 19.2.3.6 Late Write Hits A late write hit occurs when the late write buffer is valid and the address of the late write buffer matches haddr. The following table shows the possible late write hit scenarios and the result of each. 8-bit access to 0x1007 0x1007 0x0 10000000 0 16-bit access to 0x1000 0x1000 0x1 00000011 0 16-bit access to 0x1005 0x1004 0x2 01100000 1 16-bit access to 0x1007 0x1007 0x1008 0x0 0x0 10000000 00000001 0 0 32-bit access to 0x1000 0x1000 0x2 00001111 0 32-bit access to 0x1002 0x1000 0x3 00111100 1 32-bit access to 0x1003 0x1000 0x3 01111000 1 32-bit access to 0x1007 0x1004 0x1008 0x0 0x2 10000000 00000111 1 1 64-bit access to 0x1000 0x1000 0x3 11111111 0 64-bit access to 0x1003 0x1000 0x1008 0x3 0x2 11111000 00000111 1 1 Update byte 0x0 0x0 0x0 00000001 0 Update byte 0x1 0x1 0x0 00000010 0 Update bytes 0x1, 0x2 and 0x3 0x0 0x2 00001110 1 Update bytes 0x1, 0x2, 0x3 and 0x4 0x0 0x2 00001111 0 Update bytes 0x0, 0x1 and 0x3 0x0 0x2 00001011 1 Update bytes 0x3, 0x4 and 0x5 0x0 0x3 00111000 1 Update bytes 0x0, 0x1, 0x5 and 0x7 0x0 0x3 10100011 1 Table 19-8. Late Write Hit Cases Access Type haddr lwb1 addr lwb1 size Action Description Wait State? 1 64-bit read A2 A2 64 hrdata = lwb data No 2 64-bit read A2 A03 or A14 32 32bit read of missing word No 3 64-bit write A2 A*5 — store during address phase No 4 ≤ 32-bit read A03 A2 64 hrdata = lwb data 0 No 5 ≤ 32-bit read A03 A03 32 hrdata = lwb data 0 No 6 ≤ 32-bit read A03 A14 32 not a hit, actually a miss, lwb held, normal array read No 7 32-bit write A03 — — store during address phase No 8 < 32-bit write Ax5 Ax5 <size>6 array read if necessary lwb/pram_rdata merged No Table 19-7. Unaligned Writes (Continued) Transfer description HADDR HSIZE[2:0] HBSTRB[7:0] HUNALIGN |
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