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MAC7200 Datasheet(PDF) 469 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 469 Page - Freescale Semiconductor, Inc

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Platform RAM Array Controller (PRAM_CTL)
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
391
Figure 19-7. Less than 32-bit writes
19.2.3.5.3
Unaligned Writes
The PRAM_CTL controller is compliant with the ARMv6 AMBA Extensions specification with regard to
section "3.1 Byte Strobes." In essence, this document specifies that the valid byte strobes (HBSTRB[7:0])
are determined by the container which is determined by HADDR and HSIZE. The size of the transfer will
be sufficient to cover all bytes being written and will cover more bytes in the case of a mis-aligned transfer.
The address of the transfer will be rounded down to the nearest boundary of the size of the transaction.
Table 19-7 below is a replica of the two tables shown in the ARMv6 document. The 32-bit implementation
can be inferred from this table as well.
It should be noted that unaligned writes always generate read/modify/write operations in the pram
controller in order to preserve the validity of the ECC codeword.
Table 19-7. Unaligned Writes
Transfer description
HADDR
HSIZE[2:0]
HBSTRB[7:0]
HUNALIGN
8-bit access to 0x1000
0x1000
0x0
00000001
0
8-bit access to 0x1003
0x1003
0x0
00001000
0
1
234
56
7
addr y
addr z
nonseq
nonseq
idle
byte
byte
data y
data z
addr y
addr z
addr y
addr z
2'b10
2'b11
2'b01
2'b10
2'b11
2'b01
2'b11
data y
data z
data y
data z
data y
data z
hclk
haddr
htrans
hwrite
hsize
hready
hwdata
pram_addr
pram_we
pram_cs_b
pram_rdata
pram_wdata
late write buffer



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